1. Field of the Invention
The present invention relates to a read circuit for a semiconductor memory device, for serially reading data from a serial output terminal, and a semiconductor memory device.
2. Description of the Related Art
A semiconductor memory device is now frequently required to operate at high speed. With the high-speed operation, data are frequently required to be read from memory cells at high speed.
A conventional read circuit for a semiconductor memory device, for serially reading data from a serial output terminal is described. FIG. 4 illustrates the conventional read circuit.
When an address signal except for low-order two bits of a plurality of bits necessary to determine an address is input before the determination of the address, a switch circuit SW_A and sense amplifiers A1 to A4 are used and simultaneously a plurality of data signals D7 are read. After that, when an address signal except for low-order one bit of a plurality of bits necessary to determine the address is input before the determination of the address, a switch circuit SW_B and sense amplifiers A5 and A6 are used and simultaneously a plurality of data signals D6 are read.
When an address signal of all bits necessary to determine the address is input after the determination of the address, sense amplifiers A7 to A12 are used and simultaneously data signals D5 to D0 are read. The data signals D7 and D6 selected from the plurality of data signals D7 and D6 and the data signals D5 to D0 are sequentially read from a serial output terminal 200 (see, for example, Japanese Patent Translation Publication No. 2002-515628).
However, the conventional read circuit requires the four sense amplifiers A1 to A4 for reading the plurality of data signals D7, the two sense amplifiers A5 and A6 for reading the plurality of data signals D6, and the six sense amplifiers A7 to A12 for reading the data signals D5 to D0. In other words, 12 sense amplifiers are required in total, and hence a circuit scale is increased.